1. Field of the Invention
The present invention relates to a level converter circuit that converts the amplitude of a signal in a semiconductor device and a semiconductor integrated circuit device.
2. Description of Related Art
The Documents cited herein and the numbers by which will be referred to be as follows: [Document 1] JP-A-283979/1994; [Document 2] JP-A-163960/2000; and [Document 3] JP-A-139663/1997.
FIG. 4 in Document 1 shows a conventional level converter circuit including a pair of P-channel MOSFETs Q7, Q8 with cross-coupled drains and gates and a pair of N-channel MOSFETs Q11, Q12 that receive complementary signals of reduced amplitude from an input at their gates. In addition, FIG. 1 in Document 1 shows an improved version of the level converter circuit of FIG. 4, which provides a pair of N-channel MOSFETs stages Q1, Q3 or Q2, Q4 to ensure an adequate withstand voltage.
FIG. 4 (B) in Document 2 shows a level converter circuit including two P-channel MOSFET stages Q31, Q32 or Q33, Q34 and two N-channel MOSFET stages Q35, Q36 or Q37, Q38. The gates of Q35, Q37 are biased to a constant voltage at a VPERI potential. It is assumed that VPERI is the power supply potential of a circuit (LOG shown in FIG. 4) that operates with a smaller amplitude before level conversion. Q35 or Q37 limits the voltage applied between the drain and the source of Q36 or Q38 to VPERI. Similarly, Q32 or Q34 limits a voltage applied between the drain and the source of Q32 or Q33 to VDD-VPERI (VDD greater than VPERI).
FIG. 1 in Document 3 also shows a level converter circuit similar to the circuit (MOSFETs 14-17 and 19-22) shown in FIG. 4 (B) in Document 2
In a preliminary study of system-on-a-chip circuits, it was found that the internal operating voltages in existing circuits of this type are increasingly lowered in response to demands for smaller power consumption. On the other hand, external interfaces have to use the relatively high standard voltages. As such, signals must be converted across very large differences between power supply voltages. Under these circumstances, it is difficult for a conventional level converter circuit configured only with MOSFETs with high withstand voltages (that have been designed for power supply voltages for great-amplitude signals) to convert the signals. A prior art level converter circuit has difficulty in operation if the input signal voltage level becomes smaller than 1 V, such as VDD=0.75 V. This is mainly caused by a reduced difference between the threshold voltage of the input N-channel MOSFETs for driving a latch and the power supply voltage for an input signal, which makes it difficult for the input N-channel MOSFETs to operate. In addition, there is an urgent demand for system-on-a-chip circuits with lower power consumption. To meet this demand, it is important to lower the internal voltages of a system-on-a-chip circuit. However, lowering the internal operating voltage of a system-on-a-chip circuit leads to difficulties of sending and receiving signals to and from external circuits with relatively high standard voltages.
Accordingly, one object of the present invention is to achieve internal voltages smaller than 1 V without reducing external standard voltages and to provide a circuit that converts signal levels at a high speed.
In addition, substrate potentials of MOS circuits are generally controlled to lower power consumption of system LSI circuits. Lowered operating voltages of the internal control circuit, however, will make it difficult to control the substrate potentials.
Accordingly, another object of the present invention is to provide a level converter circuit that can convert a signal to one great amplitude for controlling substrates even if the operating voltages of the internal circuits are reduced.
One example of the present invention is described below. This means of the present invention provides a level converter circuit with MOSFETs having two different oxide film thicknesses (Tox) thereby having different withstand voltages. The invention uses a low-withstand-voltage MOSFET with a relatively thin gate insulating film as an input MOSFET for receiving small-amplitude signals, and a high withstand voltage MOSFET with a relatively thick gate insulating film as a withstand voltage enhancement MOSFET. The withstand voltage enhancement MOSFET has a relatively low threshold voltage.
In addition, to process signals of amplitudes as small as 1 V or less, it is preferable to provide a gate boosting circuit GBST that temporarily boosts the gate potential of the withstand voltage enhancement transistors in response to the input signal to assist the potential level conversion, and a level keeping circuit LKP that suppresses the potential of a node between the withstand-voltage-enhancement transistors and the input thin-film NMOS transistor to the withstand voltage of the input thin-film NMOS transistor. Furthermore, the increase of operating voltage range causes an unbalance between the rising and falling delay time. To avoid such an unbalance, it is preferable to add a transition detector circuit to the level converter circuit.